1. Field of the Invention
The present invention generally relates to phase and frequency detectors, and more particularly, to digital phase and frequency detectors. Even more specifically, the invention relates to a digital phase detector that is well suited for use in a digital phase locked loop.
2. Background Art
A phase locked loop is a circuit designed to minimize the phase difference between two signals. When the phase difference approaches zero, or is within a specified tolerance, the phase of the two signals is said to be “locked”. Phase locked loops (PLL's) are widely used circuits where it is necessary to have two signals which have a known relationship to one another. For example, when transmitting information from a sending device to a receiving device, it is necessary to have the local clock of the receiving device in sync with the clock of the sending device so that the information can be reliably transmitted. A PLL may be used for that purpose. PLL's have been used for a long period of time, and numerous analog examples of these circuits can be found in the literature and in many devices.
In PLL techniques, a reference clock is generated at the frequency or sub-frequencies of the received data rate, usually using a voltage-controlled oscillator (VCO). A phase detector (PD) circuit compares the phase angle between the VCO clock signal and the received data stream. The phase detector provides a control signal, which is a function of the relative phase between the VCO clock signal, and the received data signal. This control signal is used to adjust the VCO frequency until the clock signal is synchronized with the received data.
PLL's are also used in a variety of devices where the PLL can be constructed of all digital components. The all-digital approach has the benefits of being portable and scalable for other processes and applications. For example, all digital implementations of PLL's are needed for such complex circuits as memory devices. The system clock of certain types of memory devices needs to be in sync with, for example, data so that data may be reliably written to or read from the memory. PLL's are also needed when transferring data within the memory device to insure, for example, that data read out of the memory is properly presented to output pads.
A phase detector is a very important part of a PLL. The phase detector is used to provide phase discrimination and generate a control signal, which is then used to speed up or slow down the local signal so that a desired relationship between the local signal and the reference signal is obtained.
Various approaches to digital phase detectors have been attempted; however, it is believed that these approaches can be improved. For instance, with traditional digital phase detectors, it is difficult to achieve a control signal that accurately indicates the phase difference between the local and reference signals when the loop is close to “lock.” Thus, the need exists for a digital phase detector that is suitable, for example, in PLLs and that can reliably produce control signals even when the phase difference between the two signals applied to the detector is very small.